Commonly known matrix display devices are such as an active matrix substrate on which TFTs (Thin Film Transistors) are formed and a liquid crystal display device including driver ICs (Integrated Circuits) for driving the TFTs.
FIG. 18 illustrates a TFT active matrix liquid crystal display device 101. This liquid crystal display device 101 is provided with a gate driver 102 which is a circuit for driving rows of the matrix and a source driver 103 which is a circuit for driving columns of the matrix.
On a transparent substrate, a plurality of gate lines Gn, Gn+1 . . . (correctively termed G) driven by the gate driver 102 and a plurality of source lines Sn, Sn+1 . . . (correctively termed S) driven by the source driver 103 are formed. The gate lines G are orthogonal to the source lines S. At each of the intersections of the gate lines G and the source lines S, a pixel PIX is provided. This pixel PIX includes a TFT 104, a liquid crystal 105, and an auxiliary capacity 106. In each of the areas circumscribed by the gate lines G and the source lines S, a pixel electrode (cf. FIG. 19) 107 which is one of two electrodes of the liquid crystal 105 and the auxiliary capacity 106 is formed. This pixel electrode 107 is connected to a drain electrode of the TFT 104. In a pixel PIX at an n-th row and n-th column, a source electrode of the TFT 104 is connected to a source line Sn of the n-th row, and a gate electrode of the TFT 104 is connected to a gate line Gn of the n-th column.
In this manner, focusing attention on the relationship between the gate lines G and the pixel electrodes 107 in the liquid crystal display device 101 in which the pixels PIX are formed, it is noticed that the liquid crystal display device 101 in FIG. 18 is a so-called bottom-gate liquid crystal display device in which the gate line Gn of the n-th row is provided below the pixel electrode 107 of the n-th row. Further, as illustrated in FIG. 19, between the pixel electrode 107 and the gate line Gn and between the pixel electrode 107 and the gate line Gn−1, parasitic capacitances Cgd1 and Cgd2 are formed, respectively. In the pixel of the first row, a gate line G0 corresponding to the foregoing gate line Gn−1 of the pixel of the n-th pixel is not provided so that a parasitic capacitance corresponding to the foregoing parasitic capacitance Cgd2 is not formed. FIG. 18 illustrates the difference between an equivalent circuit of the pixel of the first row (line G1) in which the parasitic capacitance Cgd2 is not formed and an equivalent circuit of the pixel of the second low and later (Gn (n≠1)) in which the parasitic capacitances Cgd1 and Cgd2 are both formed.
In the meantime, as illustrated in FIG. 20, a gate signal having an amplitude Vgpp is serially supplied to the gate lines G, and this gate signal causes a drain level of the TFT 104 to vary. That is to say, in the pixel PIX of the n-th row, via the parasitic capacitance Cgd2, the gate signal of the gate line Gn−1 varies the drain level of the TFT 104 as much as ΔV2, and via the parasitic capacitance Cgd1, the gate signal of the gate line Gn varies the drain level of the TFT 104 as much as ΔV1.
Here, provided that the capacity of the liquid crystal of the pixel PIX is Clc and the auxiliary capacity is Ccs, the above-mentioned values ΔV2 and ΔV1 are expressed as follows.ΔV1=Vgpp×{Cgd1/(Clc+Ccs+Cgd1+Cgd2)}ΔV2=Vgpp×{Cgd2/(Clc+Ccs+Cgd1+Cgd2)}
Then the value ΔV1 generated by the gate signal of the gate line Gn of the same stage causes a center value Vcom of an amplitude of the drain level of the TFT 104 to be ΔV1 lower than a center value Vsc of an amplitude of a source signal. The value ΔV2 generated by the gate signal of the gate line Gn−1 of the previous stage causes an effective value of a voltage supplied to the liquid crystal 105 to increase.
As described above, in the pixel PIX of the first row, the gate line G0 of the previous stage, which forms the parasitic capacitance Cgd2, is not provided. For this reason, the value ΔV2 is not generated and this causes the effective value of the voltage supplied to the liquid crystal 105 in the pixel PIX of the first row to be lower than the effective values supplied to the respective pixels PIX of the remaining rows. Due to this difference of the effective values, the driving conditions of the display device deteriorates such that the value ΔV2 becomes large or the temperature becomes too high or low, and thus the brightness of the pixel PIX of the first row looks different from the brightness of the remaining pixels PIX. For instance, when normally while liquid crystal is adopted, the first line looks like a bright line.
To solve this problem, for instance, U.S. Pat. No. 5,867,139 (published on Feb. 2, 1999) and Japanese Laid-Open Patent Application No. 8-43793/1996 (published on Feb. 16, 1996) teach that, in a bottom-gate panel, a dummy line G0 for compensating asymmetry between the pixel of the first row and the remaining pixels is provided in the vicinity of the pixel of the first row and outside of an effective display area. The gate lines G1-Gm are driven by respective gate signal supplied from output terminals OG1-Ogm, and the added dummy line G0 and a gate line Gm of m-th (last) row are connected in a parallel manner so that these lines are simultaneously driven. Hereinafter, this technique is termed a conventional art 1.
FIG. 21 illustrates a gate driver 102 of the conventional art 1. This gate driver 102 is arranged in such a manner that a plurality of driver ICs 112 mounted on a TCP (Tape Carrier Package) by a TAB (Tape Automated Bonding) method are cascaded. The gate driver 102 connects a liquid crystal panel 113, on which pixels PIX, gate lines G, and source lines S are formed, with a printed board 114. Each of the driver ICs 112 includes 256 output terminals OG1-OG256. The figure illustrates a case that 3 driver ICs 112 are cascaded.
In the driver IC 112, via the printed board 114, a gate start pulse signal GSP is supplied to a terminal GSPin and a gate clock signal GCK is supplied to a terminal GCKin. Further, in the driver IC 112, the gate start pulse signal GSP, which has been shifted by an internal shift register, is outputted from a terminal GSPout, and supplied to a terminal GSPin of a driver IC 112 of the next stage, via the printed board 114. From a terminal OG256 of the last line of the driver IC 112 of the last stage, a line extends not only to the gate line G but also to the top of the liquid crystal panel 113 via the printed board 114. This line extending to the top of the liquid crystal panel 113 is the dummy line G0. With this arrangement, the dummy line G0 and the gate lines G1-G768 are formed.
FIG. 22 illustrates respective timing charts of the signals in the gate driver 102 in FIG. 21. The gate start pulse signal GSP is shifted at timings of the gate clock signal GCK, and in the course of the shifting, the gate signals are serially supplied from the terminals OG1, OG2, . . . , OG256 to the respective gate lines G. When the gate signal is outputted from a terminal OG256 of one of the driver ICs 112, the gate start pulse signal GSP is supplied from the terminal GSPout to a terminal GSPin of the driver IC 112 of the next stage.
However, this conventional art 1 has such a problem that only a driver circuit of an output terminal OGm, which drives a gate line Gm of an m-th (last) line, is under substantially doubled load, so that the waveform of the gate signal is blunted. Further, as in FIG. 21, since a bypass line for connecting the dummy line G0 and the gate line Gm via the printed board 114 is required, the liquid crystal panel 113 and the flexible printed board become intricate. To reduce costs, weight, and thickness of liquid crystal panels, it has been popular to adopt such an arrangement that a printed board, a flexible printed board, and connecter on the gate side are eliminated and power supply lines and signal lines on the side of a gate driver are formed on a liquid crystal panel and a gate driver TCP (hereinafter, this arrangement will be referred to as a gate substrate omission arrangement). In this arrangement, the power supply lines and signal lines connected to the gate driver are formed as a single-layer wiring pattern from the side of the source driver. Thus, this arrangement cannot allow the space for the line from the last m-th line to the dummy line G0 as in FIG. 21.
In this connection, as FIG. 23 illustrates, a gate driver IC in which the number of output terminals is increased in order to independently drive the dummy line G0 has been developed for solving the above-described problem. Hereinafter, this gate driver IC will be referred to as a conventional art 2. In the arrangement shown in FIG. 23, a driver IC 122 of each TCP 121 has terminals OG0-OG257. The number of the terminals of this driver IC 122 is larger than the number of the terminals of the aforementioned driver IC 122 in FIG. 21. In each of the driver ICs 122 of the respective stages, the terminals OG1-OG256 are connected to respective gate lines G. In the driver IC 122 of the first stage, the terminal OG0 is connected to a dummy line G0, while in the driver ICs 122 of the second and third stages, the terminals OG0 and OG257 are not used. Also in this arrangement, a gate start pulse signal GSP and a gate clock signal GCK are supplied via a printed board 124. However, since the dummy line G0 is driven using the terminal OG0 of the driver IC 122, it is unnecessary to provide a line for the dummy line G0, which extends from the driver IC 122 of the last stage to the top of a liquid crystal panel 123 via the printed board 124.
FIG. 24 illustrates timing charts of respective signals of the gate driver 102 in FIG. 23. First, a gate signal is supplied to the terminal OG0, and then the gate start pulse signal GSP is serially shifted. After the gate signal is outputted from the terminal OG 256, the gate start pulse signal GSP is supplied to the driver IC 122 of the next stage. Subsequently, from the terminal OG1 of this driver IC 122, the gate signal is outputted.
As illustrated in FIG. 25, this conventional art 2 can be adopted to a gate substrate omission arrangement in which lines to driver ICs 122 are formed only on a TCP 121 and a liquid crystal panel 123 so as not to pass through a printed board 124 as in FIG. 24. Also in this case, it is unnecessary to provide a lengthy line for a dummy line G0. On this account, the conventional art 2 makes it possible to realize and mass-produce a liquid crystal display device with the gate substrate omission arrangement.
However, according to the conventional art 2, it is necessary to supply the gate start pulse signal GSP, which is for supplying the output for the dummy line G0, to the gate driver 102. This gate start pulse signal GSP has to be supplied before an input data signal DATA-in and a data enable signal ENAB are supplied to a timing control ASIC which generates a signal for controlling the drive of the gate driver 102 and the source driver 103.
There are two controlling methods using the timing control ASIC, namely, a timing control method (hereinafter, HV mode) using vertical and horizontal synchronizing signals and a timing control method (hereinafter, V-ENAB mode) which only uses the data enable signal ENAB so as not to use the vertical and horizontal synchronizing signals. Referring to FIGS. 26(a)-26(f) and 27(a)-27(f), the HV mode and the V-NAB mode will be described.
First, the HV mode is described with reference to timing charts in FIGS. 26(a)-26(f).
FIG. 26(a) illustrates signals for horizontal drive, which are supplied to the timing control ASIC. The figure shows the timings of the signals in one horizontal period. In accordance with the timing of the input of the clock signal CK, the data enable signal ENAB goes high at 296-th clock from the input of a horizontal synchronizing signal Hs, and sets of data D1, D2, . . . , D1024 for one horizontal period are supplied. FIG. 26(b) illustrates signals for vertical drive, which are supplied to the timing control ASIC. The figure shows the timings of the signals in one vertical period. The data enable signal ENAB goes high after 35 horizontal periods have past from the input of a vertical synchronizing signal Vs, and during horizontal periods corresponding the rises of the data enable signal ENAB, respective sets of data DH1, DH2, . . . , DH 768 for one horizontal period of the input data signal DATAin are supplied.
FIG. 26(c) illustrates signals for horizontal drive, which are supplied from the timing control ASIC. To the source driver 103, the timing control ASIC supplies: the sets of data DH1, DH2, . . . , DH768; a liquid crystal drive inversion signal REV for reversing a signal level in each horizontal period; a source start pulse signal SSP for carrying out shifting in the source driver 103; and a latch strobe signal LS for latching the sets of data sampled in accordance with the shift timings of the source start pulse signal SSP, and outputting the latched sets of data to the respective source lines S. With this arrangement, the output waveforms from the source driver 103 are arranged as in FIG. 26(d).
FIG. 26(e) illustrates signals for vertical drive, which are supplied from the timing control ASIC. To the gate driver 102, the timing control ASIC outputs: the gate start pulse signal GSP for outputting the gate signals to cause the sets of data DH1, DH2, . . . , DH768, which are supplied from the source driver 103, to be serially supplied to the pixels of the respective rows; and the gate clock signal GCK for shifting the gate start pulse signal GSP. With this arrangement, as illustrated in FIG. 26(f), the gate driver 102 serially supply the gate signals, which are pulses, to the gate lines G.
In this manner, in the HV mode, a predetermined number of pulses of the horizontal synchronizing signal Hs, each having a predetermined length of time, is counted from the input of the vertical synchronizing signal VS, and subsequently the data enable signal ENAB and the input data signal DATAin are supplied. Thus, in the HV mode, from the supplied vertical synchronizing signal Va and horizontal synchronizing signal Hs, it is possible to generate the gate start pulse signal GSP at the timing of driving the dummy line G0 before driving the gate line G1.
Next, the V-ENAB mode will be described with reference to timings charts in FIGS. 27(a)-27(f).
FIG. 27(a) illustrates signals for horizontal drive, which are supplied to the timing control ASIC. The figure shows the timings of the signals in one horizontal period. No horizontal synchronizing signal is provided, and the data enable signal ENAB is supplied at a timing during the clock signal CK is supplied so that sets of data D1, D2, . . . , D1024 for one horizontal period are supplied. FIG. 27(b) illustrates signals for vertical drive, which are supplied to the timing control ASIC. Neither the vertical synchronizing signal nor the horizontal synchronizing signal are provided, and a length of the data enable signal ENAB supplied at a timing corresponds to a length during which the source driver 103 samples the data DH1, DH2, . . . , DH768 of one horizontal period.
FIGS. 27(c)-27(f) are identical with FIGS. 26(c)-26(f), except that the timings of the signals outputted from the timing control ASIC are determined with reference to the input timing of the data enable signal ENAB.
FIG. 28 illustrates a timing control ASIC 108, as an example of a timing control ASIC controlled in the V-ENAB mode. In this timing control ASIC 108, a separation/control section 108a separates a reference timing for horizontal drive and a reference timing for vertical drive from the supplied data enable signal ENAB and clock signal CK. A horizontal counter 108b starts to count the clocks of the clock signal CK from the reference timing for horizontal drive. A vertical counter 108c starts to count rising edges of the ENAB signal from the reference timing of vertical drive. In accordance with the result of the counting by the horizontal counter 108b, a horizontal signal timing generation block 108d generates and outputs the gate clock signal GCK, the latch strobe signal LS, the source clock signal SCK, and the source start pulse signal SSP. Also, in accordance with the result of the counting by the vertical counter 108c, a vertical signal timing generation block 108e generates and outputs the gate start pulse signal GSP. Further, in accordance with the results of the counting by the horizontal counter 108b and vertical counter 108c, a liquid crystal drive inversion signal generation block 108f generates and outputs the liquid crystal drive inversion signal REV. The input data signal DATAin is supplied to an input buffer 108g, and as output data, the input data signal DATAin is outputted from an output buffer 108h. 
In this manner, in the V-ENAB mode, the vertical and horizontal synchronizing signals are not supplied to the timing controller ASIC as in the case of the HV mode. For this reason, the gate start pulse signal GSP has to be generated from a pulse of the data enable signal ENAB supplied at the timing of inputting the data DH1 of the first line.
Thus, according to the conventional art 2, since it is not possible to generate the gate start pulse signal GSP to cause a signal for driving the dummy line G0 to be outputted before the gate signal of the gate line G1, it is not possible to perform the operation in the V-NAB mode. As the operation in the V-NAB mode is often required these days, this problem requires urgent solution.
To solve the problems of the conventional arts 1 and 2, US Patent Application No. 2001/0050678 A1 (published on Dec. 13, 2001) teaches that the internal mechanism of a gate driver IC is modified so that gate signals are serially outputted in an order different from the order of providing terminals. FIG. 29 shows this arrangement. In a gate driver 102 in the figure, driver ICs 132 are provided instead of the driver ICs 122 of the gate driver 102 in FIG. 23. The internal mechanism of the driver IC 132 is illustrated in FIG. 30. A gate start pulse signal GSP is transferred in an internal shift register in the order of R1→R2→ . . . →R256→R0. Further, as illustrated in FIG. 31, simultaneously with the drive of a last gate line G256 by a terminal OG256 for transferring the gate start pulse signal GSP to the R256, the gate start pulse signal GSP is supplied from a terminal GSPout to the driver IC 132 of the next stage. Then at the timing of driving the dummy line G0 of the previous stage, a gate line G257 is driven by a terminal OG1 of the driver IC 132 of the next stage. Hereinafter, this arrangement will be referred to as a conventional art 3.
However, since the driver IC 132 of the gate driver 102 of the conventional art 3 has to be specially arranged to perform the gate output in the order different to the order of the output terminals, it is impossible to adopt a conventional driver IC which perform the gate output in the order corresponding to the order of the output terminals. That is to say, illustrating this arrangement with reference to FIG. 29, the driver IC 132 of the first stage cannot be a driver IC which outputs gate signals in the order of the output terminals OG0→OG1→ . . . →OG256. Thus, to adopt the conventional art 3, it is necessary to newly develop driver ICs corresponding to various resolutions, and this requires considerable time and expense. As in the foregoing description, it has been required to develop a method of driving a dummy line G0, adopting a conventional driver IC which drives in the order corresponding to the order of output terminals.